1. Field of Invention
The present invention relates to a manufacturing method for integrated circuit dielectric layer. More particularly, the present invention relates to the manufacturing of a nitride-doped dielectric layer in integrated circuit.
2. Description of Related Art
Following the trend in device miniaturization, thinner and thinner films are now employed in the production of CMOS. One consequent of this is the increase in electric field strength in a gate dielectric layer. Hence, quality of the gate dielectric layer is of growing importance. When boron ions are implanted into a polysilicon gate electrode to form a P.sup.+ doped layer, some of the boron ions will penetrate through the polysilicon gate electrode causing a breakdown of the dielectric layer. As soon as this happens, the boron ions will penetrate through the dielectric layer and end up in the silicon substrate, thereby affecting the quality of the transistor. The situation is bound to get worse because thinner and thinner films are now being designed as a result of device miniaturization. In general, doping nitrogen oxides material into a gate oxide layer is able to increase the quality of the gate oxide layer and prevent boron ions penetrating through the gate oxide layer into the silicon substrate. In addition, the presence of nitride ion in the gate oxide layer is also capable of containing a flatband voltage shift. The most commonly used method for nitrogen oxides doping is to pass a gaseous mixture having a definite ratio of nitrogen monoxide (NO) or nitrous oxide (N.sub.2 O) or ammonia (NH.sub.3) to oxygen into a furnace, and then doping in a furnace using a furnace oxidation method or a rapid thermal process (RTP). However, it is very difficult to obtain a quality nitrogen oxides doping using a conventional production technique.
FIG. 1a is a cross-sectional view showing a transistor undergoing a normal boron implant operation. As shown in FIG. 1a, a silicon substrate 100 is provided. The silicon substrate 100 has a pair of source/drain regions 102 and 104, and a gate oxide layer 106a above the substrate 100 located between the source/drain regions. Furthermore, there is a gate electrode 108 above the gate oxide layer 106a. As seen from FIG. 1a, when the gate electrode 108 undergoes a boron penetration implant, quality of the gate oxide layer 106a is of great importance. This is because whether or not the boron ions will end up in the substrate 100 and affect the quality of the transistor depends very much on the ability of boron ions to pass through the gate oxide layer 106a.
FIG. 1b is a cross-sectional view showing the gate terminal of a transistor undergoing a boron implant operation according to a method proposed by E. Hasegawa et al. In an IEEE article published in 1995 with the title "The Impact of Nitrogen Profile Engineering on Ultra-Thin Nitrided Oxide Films for Dual-Gate CMOS ULSI", E. Hasegawa et al has proposed a method for producing a nitride-doped gate oxide layer. First, a substrate 100 is provided. Next, a rapid thermal oxidation is conducted at a temperature of about 700.degree. C. to 1050.degree. C. in an atmosphere of ammonia. Then, a rapid thermal oxidation is again conducted at a temperature of about 950.degree. C. to 1150.degree. C. in an atmosphere of dry oxygen to form a gate oxide layer 106b. A curve a showing the concentration gradient of doped nitride ions is drawn in FIG. 1b. In curve a, concentration of nitride ions is the highest near the oxide layer/gate electrode interface. Thereafter, a gate electrode 108 is formed over the gate oxide layer 106b. Subsequently, conventional techniques are used to form the final transistor structure. According to the above article, the gate oxide layer 106b formed by the proposed method is able to prevent implanted boron ions from diffusing into the dielectric layer finally ending up in the silicon substrate. Moreover, the presence of the charge-carrying ions in the gate oxide layer 106b can provide three-fold increase in the charge-to-breakdown (Qbd) value of the dielectric layer. However, the above method will result in a rather unstable interface between the gate oxide layer and the silicon substrate.
FIG. 1c is a cross-sectional view showing the gate terminal of a transistor undergoing a boron implant operation according to a method proposed by L. K. Han et al. Because a structural transition layer (STL) between an oxide layer and silicon substrate is becoming more unstable as the oxide layer gets thinner, increasing nitride ions in the oxide layer is able to stabilize the structural transition layer. In an IEEE article published in 1994 with the title "Polarity Dependence of Dielectric Breakdown in Scaled SiO.sub.2," by L. K. Han, a method of improving the situation is proposed. First, a silicon substrate 100 is provided. Next, a rapid thermal oxidation is performed at a temperature of about 1050.degree. C. in the presence of pure nitrous oxide. At the same time, a furnace oxidation in the presence of dry oxygen is also performed at a temperature of about 850.degree. C. to form a gate oxide layer 106c. As shown in FIG. 1c, a curve b showing the concentration gradient of doped nitride ions inside the gate oxide layer 106c and the substrate 100 is drawn. As shown in curve b, concentration of nitride ions is the highest near the oxide layer/silicon substrate interface, therefore, the structural transition layer there can be stabilized. Thereafter, a gate electrode 108 is formed over the gate oxide layer 106c. Subsequently, conventional techniques are used to form the final transistor structure.
FIG. 1d is a cross-sectional view showing the gate terminal of a transistor undergoing a boron implant operation according to a method proposed by H. S. Momose et al. In an IEEE article published in 1994 with the title "Electrical Characteristics of Rapid Thermal Nitrided-Oxide Gate n- and p-MOSFET's with Less Than 1 Atom % Nitrogen Concentration", H. S. Momose et al has discovered a similar result as L. K. Han, and proposed that a nitride concentration of about 0.5% at the oxide layer/silicon substrate interface is optimal for the electrical property and quality of the gate oxide/silicon interface. As shown in FIG. 1d, the method is to provide a silicon substrate 100, then a rapid thermal oxidation is performed at a temperature of about 800.degree. C. to 1000.degree. C. in the presence of ammonia and using hydrochloric acid for gate oxidation. Thereafter, a rapid thermal oxidation is again performed at about 800.degree. C. to 1000.degree. C. in the presence of oxygen. Finally, a rapid thermal oxidation is performed at a temperature of about 800.degree. C. to 1000.degree. C. in the presence of ammonia to form an oxide layer 106d. As shown in FIG. 1d, a curve c showing the concentration gradient of doped nitride ions inside the gate oxide layer 106d and the substrate 100 is drawn. As shown in curve c, concentration of nitride ions is the highest at about 0.5% near the oxide layer/silicon substrate interface. Thereafter, a gate electrode 108 is formed over the gate oxide layer 106d. Subsequently, conventional techniques are used to form the final transistor structure.
The conventional method of heavily doping nitride ions in region between the polysilicon layer and the oxide layer as proposed by E. Hasegawa is only able to block the penetration of boron ions into the silicon substrate. With regard to the silicon substrate/oxide layer interface, this method does not offer much assistance. On the other hand, the method proposed by L. K. Han is used to deposit high concentration of nitride ions in the transition layer between the oxide layer and the silicon substrate, only the oxide layer/silicon substrate interface will be stabilized and will degrade electrical property with higher nitrogen concentration. There will be little effect on the problem of boron penetration. The method of doping nitride ions up to 0.5% at the oxide/substrate interface adopted by H. S. Momose also faces the problem of boron penetration.
In light of the foregoing, there is a need to provide an improved method of forming a gate oxide layer.